1) Field of the Invention
The present invention relates to a technology for supporting designing of large scale integrated circuit (LSI).
2) Description of the Related Art
In designing LSI's, there is a requirement to increase working efficiency by shortening the duration required for designing, and to mount the system on one chip. FIG. 1 is an explanatory diagram of one example of a conventional design flow. In FIG. 1, a designer creates a user net list 2701 which represents a logic circuit at a gate level. The designer creates an interface (I/F) file 2702 in order to carry out test synthesis. This file 2702 includes boundary scan information representing a connection relationship between a test circuit and a hard macro in the user net list 2701, clock connection information at the time of a test, memory simultaneous test information, internal scan chain information, phase locked loop (PLL) terminal information, test terminal information, and the like.
The I/F file 2702 is captured into the user net list 2701 and a test circuit is inserted, so that the test synthesis is carried out (step S2701). A test-synthesized net list 2703 is laid out based on arrangement/wiring area information in a frame 2704 (step S2702). FIG. 2 is an explanatory diagram of a conventional frame. The frame 2800 is information representing areas where cells and nets can be arranged and wired on the layout of the LSI. In FIG. 1, the laid-out data are output as graphic data system (GDS) to a later LSI development step, and are output as a net list 2705 to a user. A test pattern 2706 is created based on the net list 2705 (step S2703), and the net list can be utilized also as a failure analysis net list.
In the process flow, rule checks R1 to R3 on the net list are made before and after the test synthesis, and after the layout. At the rule check R1 before the test synthesis, the check is made whether the user net list 2701 can be test-synthesized by using a test synthesis tool (step S2701). At the rule check R2 after the test synthesis, the check is made whether setting in the test-synthesized net list 2703 is correct. At the rule check R3 after the layout, the check is made whether a test circuit is influenced such that the logic in the test circuit is rewritten. When an error occurs at the rule check R1, redesign on the user net list 2701 is required. When an error occurs at the rule check R2, the test synthesis is again required. When an error occurs at the rule check R3, the layout is again required.
Due to the layout (step S2702), a plurality of random access memories (RAM) are developed on the frame 2800. FIG. 3 is an explanatory diagram of a state that a plurality of RAMs is laid out on the frame 2800. In FIG. 3, a RAM 2091 includes a core 2911 where a bit/word configuration is 20×1024, a RAM 2902 includes a core 2912 where a bit/word configuration is 40×512, and a RAM 2903 includes a core 2913 where a bit/word configuration is 80×256. Controllers 2921 to 2923 are provided on input sides of the RAMs 2901 to 2903, respectively. When tests are conducted for on the RAMs 2091 to 2903, an initializing signal MDI is input so that the tests are conducted for the RAMs 2901 to 2903. Output data MDO are output from the RAMs 2901 to 2903 via a selector 2930.
The layout (step S2702) makes it possible to suitably prepare and wire various boundary scan registers (BSR) for input, output, bus, 3-STATE, clock, shared input/scan in, shared output/scan out, and the like on the frame 2800 according to a configuration of an I/O area of the LSI.
Due to the layout (step S2702), BSR cells are sequentially arranged so that a boundary scan chain can be formed. FIG. 4 is an explanatory diagram of the boundary scan chain formed by sequentially arranging the BSRs. In FIG. 4, the boundary scan chain 3000 is formed by sequentially arranging a plurality of BSR cells 3001 including BSRs. The boundary scan chain 3000 is cut at a portion near a Test Access Port (TAP) controller 3010. Due to this cutting, a cut area 3005 is formed between a BSR cell 3001S as a starting point of the boundary scan chain 3000 and a BSR cell 3001E as an end point. A control signal line of the TAP controller 3010 and a test signal line 3020 are connected so as to pass through the cut area 3005.
In the design made by the process flow, however, the test-synthesized net list 2703 is used so as to the layout is carried out (step S2702). At the test synthesis (step S2701), therefore, a test circuit should be inserted after contents of the test-synthesized layout are assumed. Accordingly, design efficiency is deteriorated, and realization of system on chip (SOC) is inhibited.
In the process flow, the test circuit is inserted by the test synthesis before the layout (step S2702). When the insertion of the test circuit is not considered at the time of logic design or is not sufficiently considered, however, timing convergence in the layout should be again carried out due to the circuit added by inserting the test circuit. As a result, increase in a number of steps causes a longer design period.
When the user net list 2701 is timing-converged, the timing convergence is again required due to the insertion of the test circuit in the test synthesis, and thus the increase in a number of the steps causes the lengthening of the design period. Further, when the test synthesis condition is largely different from an actual arrangement status, the wiring length increases and accordingly a test operating frequency is lowered.
When the designer creates the I/F file 2702 for the test synthesis, the test synthesis cannot be accurately carried out due to an artificial mistake such as an inputting error. A number of the step from the test synthesis to the test pattern increases, thereby causing the lengthening of the design period.
In the process flow, since the three rule checks (R1 to R3) are made, a number of the steps in the process flow increases, thereby causing the lengthening of the design period. When an error occurs in the rule check R1, the user net list should be redesigned, and when an error occurs in the rule check R2, the test synthesis is again required. Further, when an error occurs in the rule check R3, the layout is again required, thereby causing the lengthening of the design period.
In the process flow, the test circuit is inserted by the test synthesis before the layout (step S2702), but the test circuit influences the timing of a system mode. Accordingly, as the designer has to design the system mode with the insertion of the test circuit in mind, a strain on the designer is increased.
The RAMs 2901 to 2903 shown in FIG. 3 use the cores 2911 to 2913 having the different bit/word configurations, respectively, but the differences in the bit/word configuration among the RAMs 2901 to 2903 restrain a combination of simultaneous tests. This causes the lengthening of the test period. Further, in the process flow, since the test pattern is created for every macro cell of the RAMs, PLL, and the like mounted on the user net list 2701, it takes a long time to create the test patterns. This causes the lengthening of the design period.
When various BSRs are suitably prepared and wired, the flexibility in design increases, but the time for the design work also increases. Meanwhile, when control signal wiring information between the timing-adjusted TAP controller and BSR is added to the frame, the configuration of the control terminals is different according to types of the BSRs to be used, thereby decreasing the flexibility in design.
In FIG. 4, when the BSR cells 3001 are sequentially arranged, the sequential arrangement area of the boundary scan chain 3000 is cut in order to create the starting point and the end point of the boundary scan chain 3000 or to draw a control signal line of the TAP controller 3010. In this case, even if the sequential arrangement area is cut, the BSR cell 3001S as the starting point and the BSR cell 3001E as the end point of the boundary scan chain 3000 are limited to be on the cut position. Accordingly, when the wiring property between the BSR cell 3001S as the starting point and the BSR cell 3001E as the end point of the boundary scan chain 3000, and the TAP controller 3010 is considered, the TAP controller 3010 should be arranged near the cut area 3005 of the boundary scan chain 3000.
The terminal of the TAP controller 3010 should be similarly arranged near the cut area 3005 of the boundary scan chain 3000. Since the control signal line of the TAP controller 3010 and the test signal line 3020 are wired on the cut area 3005 of the boundary scan chain 3000, the cut area is excessively occupied when the control signal line and the test signal line 3020 increase. This inhibits the wiring on the area. As a result, the flexibility in design is deteriorated on the cut area 3005 of the boundary scan chain 3000 and its vicinity.